LTC3839 Datasheet, PDF (14/50 Pages) Linear Technology – Fast, Accurate, 2-Phase, Single-Output Step-Down DC/DC Controller

LTC3839
OPERATION (Refer to Functional Diagram)
Power Good and Fault Protection
The PGOOD pin is connected to an internal open-drain
N-channel MOSFET. An external resistor or current
source can be used to pull this pin up to 6V (e.g., V_OUT
or DRV_CC). Overvoltage or undervoltage comparators
(OV, UV) turn on the MOSFET and pull the PGOOD pin low
when the feedback voltage is outside the ±7.5% window
of the 0.6V reference voltage. The PGOOD pin is also
pulled low when the RUN pin is below the 1.2V threshold
(hysteresis applies), or in undervoltage lockout (UVLO).
Note that feedback voltage is sensed differentially through
V_OUTSENSE+ with respect to V_{OUTSENSE–}.
When the feedback voltage is within the ±7.5% window,
the open-drain NMOS is turned off and the pin is pulled
up by the external source. The PGOOD pin will indicate
power good immediately after the feedback is within the
window. But when a feedback voltage of a channel goes
out of the window, there is an internal 50μs delay before
its PGOOD is pulled low. In an overvoltage (OV) condition,
M_T is turned off and M_B is turned on immediately without
delay and held on until the overvoltage condition clears.
Foldback current limiting is provided if the output is below
one-half of the regulated voltage, such as being shorted to
ground. As the feedback approaches 0V, the internal clamp
voltage for the ITH pin drops from 2.4V to around 1.3V,
which reduces the inductor valley current level to about
30% of its maximum value. Foldback current limiting is
disabled at start-up.
Frequency Selection and External Clock
Synchronization
An internal oscillator (clock generator) provides phase-
interleaved internal clock signals for individual channels
to lock up to. The switching frequency and phase of each
switching channel are independently controlled by adjust-
ing the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector, and
the time interval of the one-shot timer is adjusted on a
cycle-by-cycle basis, so that the rising edge of the top
MOSFET turn-on is always trying to synchronize to the
internal reference clock signal for the respective channel.
The frequency of the internal oscillator can be programmed
from 200kHz to 2MHz by connecting a resistor, R_T, from the
RT pin to signal ground (SGND). The RT pin is regulated
to 1.2V internally.
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTC3839 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within ±30% of the
internal oscillator frequency for successful synchroniza-
tion. The clock input levels should be no less than 2V for
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
3839fa
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