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LTC3805-5_15 Datasheet, PDF (14/20 Pages) Linear Technology – Adjustable Frequency Current Mode Flyback/ Boost/SEPIC DC/DC Controller
LTC3805-5
APPLICATIONS INFORMATION
Overcurrent Threshold Adjustment
Figure 5 shows the connection of the overcurrent pin, OC,
along with the ISENSE pin and the current sense resistor
RSENSE located in the source circuit of the power NMOS
which is driven by the GATE pin. The internal overcurrent
threshold on the OC pin is set at VOCT = 100 mV which is the
same as the peak current sense voltage VI(MAX) = 100 mV on
the ISENSE pin. The role of the slope compensation adjust-
ment resistor RSLOPE and the slope compensation current
ISLOPE is discussed in the prior section. In combination with
the overcurrent threshold adjust current IOC = 10µA, an
external resistor ROC can be used to lower the overcurrent
trip threshold from 100mV. This section describes how
to pick ROC to achieve the desired performance. In the
discussion that follows be careful to distinguish between
“current limit” where the converter continues to run with
the ISENSE pin limiting current on a cycle-by-cycle basis
while the output voltage falls below the regulation point
and “overcurrent protection” where the OC pin senses an
overcurrent and shuts down the converter for a timeout
period before attempting an automatic restart.
One overcurrent protection strategy is for the converter
to never enter current limit but to maintain output volt-
age regulation up to the point of tripping the overcurrent
protection. Operation at minimum input voltage VIN(MIN)
hits current limiting for the smallest output current and
is the design point for this strategy.
First, for operation at VIN(MIN), calculate the duty cycle Duty
Cycle VIN(MIN) using the appropriate formula depending on
whether the converter is a boost, flyback or SEPIC. Then
GATE
LTC3805-5
ISENSE
RSLOPE
ISLOPE
ROC IOC = 10µA
OC
RSENSE
GND
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Figure 5. Circuit to Decrease Overcurrent Threshold
use Duty Cycle VIN(MIN) to calculate DVSENSE(VIN(MIN))
using the formula in the prior section. For overcurrent
protection to trip at exactly the point where current limit-
ing would begin set:
ROC(CRIT )
=
DVSENSE ( VIN(MIN))
10µA
To find the actual output current that trips overcurrent
protection, calculate the peak switch current IPK(VIN(MIN))
from:
IPK
(
VIN(MIN))
=
100mV
−
DVSENSE
RSENSE
(
VIN(MIN))
Then calculate the converter output current that corre-
sponds to IPK(VIN(MIN)). Again, the calculation depends
both on converter type and the details of converter design
including inductor current ripple. For minimum input volt-
age, ROC(CRIT) produces an overcurrent trip at an output
current just before loss of output voltage regulation and
the onset of current limiting. Note that the output current
that causes an overcurrent trip is higher for higher input
voltages but that an overcurrent trip will always occur
before loss of output voltage regulation. If desired to
meet a specific design target, an increase in ROC above
ROC(CRIT) can be used to reduce the trip threshold and
make the converter trip for a lower output current.
This calculation is based on steady-state operation. De-
pending on design, overcurrent protection can also be
triggered during a start-up transient, particularly if large
output filter capacitors are being charged as output voltage
rises. If that is a problem, output capacitor charging can
be slowed by using a larger value of SSFLT capacitor. It is
also possible to trip overcurrent protection during a load
step especially if the trip threshold is lowered by making
ROC > ROC(CRIT).
Another overcurrent protection strategy is keep the con-
verter running as current limiting reduces the duty cycle
and the output voltage sags. In this case, the goal is often
keep the converter in normal operation over as wide a range
as possible, including current limiting, and to trigger the
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