LTC3209-1 Datasheet, PDF (14/20 Pages) Linear Technology – 600mA Main/Camera LED Controller

LTC3209-1/LTC3209-2
OPERATIO
REGA, MAIN LED 8-Bit DAC Data
MSB
A7
A6
MAIN D7 MAIN D6
A5
MAIN D5
A4
MAIN D4
A3
MAIN D3
A2
MAIN D2
A1
MAIN D1
REGB, CAMERA LED 4-Bit High and 4-Bit Low DAC Data
MSB
HIGH BITS
LSB
B7
B6
B5
B4
CAM D3
CAM D2
CAM D1
CAM D0
MSB
B3
CAM D3
LOW BITS
B2
B1
CAM D2
CAM D1
REGC, AUX Data and Option Byte
MSB
C7
C6
C5
Force2x
Force1p5
Dth2
C4
C3
C2
Dth1
Scamhilo
Drop2ms
DAUX0
DAUX1
Drop2ms
Scamhilo
Dth1
Dth2
Force1p5
Force2x
AUX DAC Data (LSB)
AUX DAC Data (MSB)
1 Changes Dropout Time from 150ms to 2ms
0 Dropout Time is 150ms Unless CAMHL is Enabled and High
1 Selects CAM High Register, Disables CAMHL Pin
0 Selects CAM Low Register, Enables CAMHL Pin
0 Must Always be 0 (Test Mode)
0 Must Always be 0 (Test Mode)
1 Forces Charge Pump into 1.5x Mode, CPO Regulates at 4.6V
0 Enables Mode Logic to Control Mode Changes Based on Dropout Signal
1 Forces Charge Pump into 2x Mode, Overrides Force1p5 Signal, CPO Regulates at 5.1V
0 Enables Mode Logic to Control Mode Changes Based on Dropout Signal
C1
DAUX1
LSB
A0
MAIN D0
LSB
B0
CAM D0
LSB
C0
DAUX0
I²C Interface
The LTC3209-1/LTC3209-2 communicates with a host
(master) using the standard I²C 2-wire interface. The
Timing Diagram (Figure 5) shows the timing relationship
of the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources, such as the LTC1694 SMBus
accelerator, are required on these lines.
The LTC3209-1/LTC3209-2 is a receive-only (slave)
device.
Bus Speed
The I²C port is designed to be operated at speeds of up to
400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
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