LTC3417 Datasheet, PDF (13/20 Pages) Linear Technology – Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator

LTC3417
APPLICATIO S I FOR ATIO
V_RUN
2V/DIV
V_OUT
1V/DIV
I_L
1A/DIV
V_IN = 3.6V
V_OUT = 1.8V
R_L = 0.9Ω
200µs/DIV
Figure 2. Digital Soft-Start Out1
Soft-Start
Soft-start reduces surge currents from V_IN by gradually
increasing the peak inductor current. Power supply se-
quencing can also be accomplished by controlling the I_TH
pin. The LTC3417 has an internal digital soft-start for each
regulator output, which steps up a clamp on I_TH over 1024
clock cycles, as can be seen in Figures 2 and 3. As the
voltage on I_TH ramps through its operating range, the
internal peak current limit is also ramped at a proportional
linear rate.
Mode Selection
The MODE pin provides mode selection. Connecting this
pin to V_IN enables Burst Mode operation for both regula-
tors, which provides the best low current efficiency at the
cost of a higher output voltage ripple. When MODE is
connected to ground, pulse skipping operation is selected
for both regulators, which provides the lowest output
voltage and current ripple at the cost of low current
efficiency. Applying a voltage that is more than 1V from
either supply results in forced continuous mode for both
regulators, which creates a fixed output ripple and allows
the sinking of some current (about 1/2∆I_L). Since the
switching noise is constant in this mode, it is also the
easiest to filter out. In many cases, the output voltage can
be simply connected to the MODE pin, selecting the forced
continuous mode except at start-up.
tors. The availability of the I_TH pin not only allows optimi-
zation of the control loop behavior, but also provides a DC
coupled and AC filtered closed-loop response test point.
The DC step, rise time, and settling at this test point truly
reflects the closed-loop response. Assuming a predomi-
nantly second order system, phase margin and/or damp-
ing factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated using the percentage of overshoot seen at this
pin or by examining the rise time at this pin.
The I_TH external components shown in the Figure 4 circuit
will provide an adequate starting point for most applica-
tions. The series RC filter sets the dominant pole-zero loop
compensation. The values can be modified slightly (from
0.5 to 2 times their suggested values) to optimize transient
response once the final PC layout is done and the particu-
lar output capacitor type and value have been determined.
The output capacitors need to be selected because of
various types and values determine the loop feedback
factor gain and phase. An output current pulse of 20% to
100% of full load current having a rise time of 1µs to 10µs
will produce output voltage and I_TH pin waveforms that will
give a sense of overall loop stability without breaking the
feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUT
immediately shifts by an amount equal to ∆I_LOAD • ESR_COUT,
where ESR_COUT is the effective series resistance of C_OUT.
∆I_LOAD also begins to charge or discharge C_OUT generat-
ing a feedback error signal used by the regulator to return
V_OUT to its steady-state value. During this recovery time,
V_RUN
2V/DIV
V_OUT
1V/DIV
I_L
0.5A/DIV
Checking Transient Response
The I_TH pin compensation allows the transient response to
be optimized for a wide range of loads and output capaci-
V_IN = 3.6V
V_OUT = 2.5V
R_L = 2Ω
200µs/DIV
Figure 3. Digital Soft-Start Out2
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