LTC3417 Datasheet, PDF (11/20 Pages) Linear Technology – Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator

LTC3417
APPLICATIO S I FOR ATIO
When D1 = D2 then the equation simplifies to:
I_RMS = ₍I₁ + I₂₎ D₍1– D₎
or
I_RMS = ₍I₁ + I₂₎
( ) ^V_OUT ^V_IN ^{– V}_OUT
V_IN
where the maximum average output currents I₁ and I₂
equal the respective peak currents minus half the peak-to-
peak ripple currents:
I₁
=
I_LIM1
–
∆I_L1
2
I₂
=
I_LIM2
–
∆I_L2
2
These formula have a maximum at V_IN = 2V_OUT, where
I_RMS = (I₁ + I₂)/2. This simple worst case is commonly
used to determine the highest I_RMS.
For “out of phase” operation, the ripple current can be
lower than the “in phase” current.
In the “out of phase” case, the maximum I_RMS does not
occur when V_OUT1 = V_OUT2. The maximum typically occurs
when V_OUT1 – V_IN/2 = V_OUT2 or when V_OUT2 – V_IN/2 =
V_OUT1. As a good rule of thumb, the amount of worst case
ripple is about 75% of the worst case ripple in the “in
phase” mode. Also note that when V_OUT1 = V_OUT2 = V_IN/2
and I₁ = I₂, the ripple is zero.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours lifetime. This makes it
advisable to further derate the capacitor, or choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet the size
or height requirements of the design. An additional 0.1µF
to 1µF ceramic capacitor is also recommended on V_IN for
high frequency decoupling, when not using an all ceramic
capacitor solution.
Output Capacitor (C_OUT1 and C_OUT2) Selection
The selection of C_OUT1 and C_OUT2 is driven by the required
ESR to minimize voltage ripple and load step transients.
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
(∆V_OUT) is determined by:
∆V_OUT
≈
∆I_L
⎛
⎝⎜
ESR_COUT
+
8
•
f_O
1
• C_OUT
⎞
⎠⎟
where f_O = operating frequency, C_OUT = output capacitance
and ∆I_L = ripple current in the inductor. The output ripple
is highest at maximum input voltage, since ∆I_L increases
with input voltage. With ∆I_L = 0.35I_LOAD(MAX), the output
ripple will be less than 100mV at maximum V_IN and f_O =
1MHz with:
ESR_COUT < 150mΩ
Once the ESR requirements for C_OUT have been met, the
RMS current rating generally far exceeds the I_RIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi-
num electrolytic, special polymer, ceramic and dry tanta-
lum capacitors are all available in surface mount pack-
ages. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR(size) product of
any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP, offer
very low ESR, but have a lower capacitance density than
other types. Tantalum capacitors have the highest capaci-
tance density, but it has a larger ESR and it is critical that
the capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface tantalums, available in case heights ranging from
2mm to 4mm. Aluminum electrolytic capacitors have a
significantly larger ESR, and are often used in extremely
cost-sensitive applications provided that consideration is
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