LTC3409 Datasheet, PDF (13/16 Pages) Linear Technology – 600mA Low Vin Buck Regulator in 3mm x 3mm DFN

LTC3409
APPLICATIO S I FOR ATIO
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R_DS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (∆I_LOAD • ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT, which generates a feedback error signal.
The regulator loop then acts to return V_OUT to its steady
state value. During this recovery time V_OUT can be moni-
tored for overshoot or ringing that would indicate a stabil-
ity problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C_LOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3409. These items are also illustrated graphically in
the layout diagram of Figure 3. Check the following in your
layout.
1. Does the capacitor C_IN connect to the power V_IN
(Pins 3, 4) and GND (Exposed Pad) as close as pos-
sible? This capacitor provides the AC current to the
internal power MOSFETs and their drivers.
2. Are the C_OUT and L1 closely connected? The (–) plate of
C_OUT returns current to GND and the (–) plate of C_IN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C_OUT and a ground sense line
terminated near GND (Exposed Pad). The feedback
signals V_FB should be routed away from noisy compo-
nents and traces, such as the SW line (Pins 6), and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C_IN and the resistors R1 and R2
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point. They
should not share the high current path of C_IN or C_OUT.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to V_IN or GND.
V_IN
C_IN
V_IN V_IN
LTC3409
RUN SYNC
V_FB MODE
L1
SW
SGND GND
C1
R2
R1
V_OUT
C_OUT
3409 F03
Figure 3
3409f
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