LTC3409 Datasheet, PDF (12/16 Pages) Linear Technology – 600mA Low Vin Buck Regulator in 3mm x 3mm DFN

LTC3409
APPLICATIO S I FOR ATIO
1
BURST
PULSE SKIP
0.1
0.01 ^2.5VIN
3.6V_IN
4.2V_IN
0.001 _4.2VIN
3.6V_IN
0.0001
0.1
2.5V_IN
1
10
100
LOAD CURRENT (mA)
Figure 2
1000
3409 F02
1. The V_IN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from V_IN to ground. The resulting dQ/dt is the current
out of V_IN that is typically larger than the DC bias cur-
rent. In continuous mode, I_GATECHG = (Q_T + Q_B) where
Q_T and Q_B are the gate charges of the internal top and
bottom switches. Both the DC bias and gate charge losses
are proportional to V_IN and thus their effects will be more
pronounced at higher supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics. Thus, to obtain I²R losses, simply add R_SW to R_L
and multiply the result by the square of the average
output current.
12
Other losses including C_IN and C_OUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3409 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3409 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3409 from exceeding the maximum
junction temperature, the user will need to do a thermal
analysis. The goal of the thermal analysis is to determine
whether the operating conditions exceed the maximum
junction temperature of the part. The temperature rise is
given by:
T_R = (P_D)(θ_JA)
where P_D is the power dissipated by the regulator and θ_JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider the LTC3409 in dropout at an
input voltage of 1.6V, a load current of 600mA and an
ambient temperature of 75°C. From the typical perfor-
mance graph of switch resistance, the R_DS(ON) of the
P-channel switch at 75°C is approximately 0.48Ω. There-
fore, power dissipated by the part is:
P_D = I_LOAD2 • R_DS(ON) = 172.8mW
For the DD8 package, the θ_JA is 43°C/W. Thus, the junction
temperature of the regulator is:
T_J = 75°C + (0.1728)(43) = 82.4°C
which is well below the maximum junction temperature of
125°C.
3409f