LTC3411 Datasheet, PDF (12/20 Pages) Linear Technology – 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter

LTC3411
APPLICATIO S I FOR ATIO
The LTC3411 can also be synchronized to an external
clock signal by the SYNC/MODE pin. The internal oscillator
frequency should be set to 20% lower than the external
clock frequency to ensure adequate slope compensation,
since slope compensation is derived from the internal
oscillator. During synchronization, the mode is set to
pulse skipping and the top switch turn on is synchronized
to the rising edge of the external clock.
Checking Transient Response
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the I_TH pin not only
allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed loop re-
sponse test point. The DC step, rise time and settling at this
test point truly reflects the closed loop response. Assum-
ing a predominantly second order system, phase margin
and/or damping factor can be estimated using the percent-
age of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin.
The I_TH external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1µs
to 10µs will produce output voltage and I_TH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUT
immediately shifts by an amount equal to ∆I_LOAD • ESR,
where ESR is the effective series resistance of C_OUT.
∆I_LOAD also begins to charge or discharge C_OUT generat-
ing a feedback error signal used by the regulator to return
V_OUT to its steady-state value. During this recovery time,
V_OUT can be monitored for overshoot or ringing that would
indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C. If
R is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor C_F can
be added to improve the high frequency response, as
shown in Figure 5. Capacitor C_F provides phase lead by
creating a high frequency zero with R2 which improves the
phase margin.
12
V_IN
2.5V
TO 5.5V
C6
PGND
+
C_IN
R6
C8
PGND
SV_IN
PV_IN PGOOD
SW
LTC3411
SGND
SYNC/MODE
I_TH
V_FB
SGND
C_ITH
R_C
SGND PGND SHDN/R_T
C_C
R5
PGOOD
D1 ^L1 C_F
OPTIONAL
R1
R2
R_T
SGND SGND
GND
SGND SGND
Figure 5. LTC3411 General Schematic
+
C_OUT
V_OUT
C5
PGND
PGND
3411 F05
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