LTC1704EGN Datasheet, PDF (12/28 Pages) Linear Technology – 550kHz Synchronous Switching Regulator Controller Plus Linear Regulator Controller

LTC1704/LTC1704B
APPLICATIO S I FOR ATIO
In combination with a simple external charge pump (Fig-
ure 2), this allows the LTC1704 to completely enhance the
gate of QT without requiring an additional, higher supply
voltage.
Switcher Supply Feedback Amplifier
The LTC1704 senses the switcher output voltage at V_OUTSW
with an internal feedback op amp (see Block Diagram).
This is a real op amp with a low impedance output, 85dB
open-loop gain and 20MHz gain bandwidth product. The
positive input is connected internally to an 800mV refer-
ence, while the negative input is connected to the FB pin.
The output is connected to COMP, which is in turn con-
nected to the soft-start circuitry and from there to the
PWM generator. The switching regulator output voltage
can be obtained using the following equation:
V_OUTSW = 0.8V • ^{}1+ _RR21^{}
Unlike many regulators that use a resistor divider con-
nected to a high impedance feedback input, the LTC1704
switcher supply is designed to use an inverting summing
amplifier topology with the FB pin configured as a virtual
ground. This allows flexibility in choosing pole and zero
locations not available with simple g_m configurations. In
particular, it allows the use of “Type 3” compensation,
which provides a phase boost at the LC pole frequency
and significantly improves loop phase margin (refer to
Figure␣ 3).
COMP
FB
LTC1704
C2
R4
0.8V
FB
C3
R3
R1
R2
C1
1704 F03
V_OUTSW
Figure 3. "Type 3" Feedback Loop
Switcher Supply MIN/MAX Comparators
Two additional feedback loops in the switcher supply keep
an eye on the primary feedback amplifier and step in if the
feedback node moves ±5% from its nominal 800mV value.
The MAX comparator (see Block Diagram) activates when-
ever FB rises more than 5% above 800mV. It immediately
turns the top MOSFET (QT) off and the bottom MOSFET
(QB) on and keeps them that way until FB falls back within
5% of its nominal value. This pulls the output down as fast
as possible, preventing damage to the (often expensive)
load. If FB rises because the output is shorted to a higher
supply, QB will stay on until the short goes away, the
higher supply current limits or QB dies trying to save the
load. This behavior provides maximum protection against
overvoltage faults at the output, while allowing the circuit
to resume normal operation when the fault is removed.
The MIN comparator (see Block Diagram) trips whenever
FB is more than 5% below 800mV and immediately forces
the switch duty cycle to 90% to bring the output voltage
back into range. It releases when FB is within the 5%
window. MIN is disabled when the soft-start or current
limit circuits are active—the only two times that the output
should legitimately be below its regulated value.
Notice that the FB pin is the virtual ground node of the
feedback amplifier. A typical compensation network does
not include local DC feedback around the amplifier, so that
the DC level at FB will be an accurate replica of the output
voltage, divided down by R1 and R2 (Figure 3). However,
the compensation capacitors will tend to attenuate AC
signals at FB, especially with low bandwidth Type 1 feed-
back loops. This creates a situation where the MIN and
MAX comparators do not respond immediately to shifts in
the output voltage, since they monitor the output at FB.
PGOOD Flag
The LTC1704 comes with a power good pin (PGOOD).
PGOOD is an open-drain output, and requires an external
pull-up resistor. If both the regulators are within ±10%
from their nominal value, the transistor MPG shuts off (see
Block Diagram), and PGOOD is pulled high by the external
pull-up resistor. If any of the two outputs is more than 10%
outside the nominal value for more than 1µs, PGOOD pulls
1704bfa
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