LTC1704EGN Datasheet, PDF (11/28 Pages) Linear Technology – 550kHz Synchronous Switching Regulator Controller Plus Linear Regulator Controller

LTC1704/LTC1704B
APPLICATIO S I FOR ATIO
Overcurrent protection is achieved by limiting the drive
current. The input current at the REGILM pin programs the
current limit threshold. Refer to the Linear Regulator
Supply Current Limit Programming section for more
information on choosing R_REGILM. The linear regulator
controller employs a foldback current limit scheme for
overcurrent protection. Under a short-circuit condition,
the external NPN transistor is subjected to the full input
voltage across its collector-emitter terminal. This increases
the power dissipation of the NPN and may eventually
cause damage to the transistor. LTC1704 overcomes this
problem by using a foldback current limit scheme whereby
the available drive current is reduced as the output voltage
at REGFB pin drops. This limits the power dissipation and
prevents catastrophic damage to the external NPN.
ARCHITECTURE DETAILS
Switcher Supply Architecture
The LTC1704 switcher supply is designed to operate as a
synchronous buck converter (Figure 1). The controller
includes two high power MOSFET gate drivers to control
the external N-channel MOSFETs QT and QB. The drivers
have 0.5Ω output impedances and can carry over an amp
of continuous current with peak currents up to 5A to slew
large MOSFET gates quickly. The drain of QT is connected
to the input supply and the source of QT connected to the
switching node SW. QB is the synchronous rectifier with
its drain at SW and its source at PGND. SW is connected
to one end of the inductor, with the other end connected
to V_OUTSW. The output capacitor is connected from V_OUTSW
to PGND.
TG
SW
LTC1704
BG
PGND
V_IN
QT
L
QB
+
C_IN
V_OUTSW
+
C_OUTSW
1704 F01
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to V_IN and the
inductor current begins to increase. When the PWM pulse
completes, QT turns off and one nonoverlap interval later,
QB turns on. Now SW drops to PGND and the inductor
current decreases. The cycle repeats with the next tick of
the master clock. The percentage of time spent in each
mode is controlled by the duty cycle of the PWM signal,
which in turn is controlled by the feedback amplifier. The
master clock runs at a 550kHz rate and turns QT once
every 1.8µs. In a typical application with a 5V input and a
1.5V output, the duty cycle will be set at 1.5/5 • 100% or
30% by the feedback loop. This will give roughly a 540ns
on-time for QT and a 1.26µs on-time for QB.
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
leave the 455kHz IF band free of interference. Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1704. During
the time that QT is on, its source (the SW pin) is at V_IN. V_IN
is also the power supply for the LTC1704. However, QT
requires V_IN + V_GS(ON) at its gate to achieve minimum R_ON.
The LTC1704, needs to generate a gate drive signal at TG
higher than its highest supply voltage. To accomplish this,
the TG driver runs from floating supplies, with its negative
supply attached to SW and its power supply at BOOST.
This allows it to slew up and down with the source of QT.
LTC1704 PV_CC
PGND
BOOST
TG
SW
BG
D_CP
C_CP
V_IN
+
C_IN
QT
L
QB
V_OUTSW
+
C_OUTSW
1704 F02
Figure 1. Synchronous Buck Architecture
Figure 2. Floating TG Driver Supply
1704bfa
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