LTC3859AL Datasheet, PDF (11/44 Pages) Linear Technology – Triple Output, Buck/Buck/Boost Synchronous Controller with 28μA Burst Mode IQ

LTC3859AL
Pin Functions (QFN/TSSOP)
FREQ (Pin 1/Pin 5): The Frequency Control Pin for the
Internal VCO. Connecting the pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting the pin
to INTV_CC forces the VCO to a fixed high frequency of
535kHz. Other frequencies between 50kHz and 900kHz can
be programmed using a resistor between FREQ and GND.
The resistor and an internal 20µA source current create a
voltage used by the internal oscillator to set the frequency.
PLLIN/MODE (Pin 2/Pin 6): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG1 signal to be
synchronized with the rising edge of the external clock,
and the regulators operate in forced continuous mode.
When not synchronizing to an external clock, this input,
which acts on all three controllers, determines how the
LTC3859AL operates at light loads. Pulling this pin to
ground selects Burst Mode operation. An internal 100k
resistor to ground also invokes Burst Mode operation
when the pin is floated. Tying this pin to INTV_CC forces
continuous inductor current operation. Tying this pin to
a voltage greater than 1.2V and less than INTV_CC – 1.3V
selects pulse-skipping operation. This can be done by
connecting a 100k resistor from this pin to INTV_CC.
SGND (Pin 8/Pin 12): Small Signal Ground common to
all three controllers, must be routed separately from high
current grounds to the common (–) terminals of the C_IN
capacitors.
RUN1, RUN2, RUN3 (Pins 9, 10, 11/Pins 13, 14, 15):
Digital Run Control Inputs for Each Controller. Forcing
RUN1 below 1.17V and RUN2/RUN3 below 1.20V shuts
down that controller. Forcing all of these pins below 0.7V
shuts down the entire LTC3859AL, reducing quiescent
current to approximately 10µA.
OV3 (Pin 17/Pin 21): Overvoltage Open-Drain Logic
Output for the Boost Regulator. OV3 is pulled to ground
when the voltage on the V_FB3 pin is under 110% of its set
point, and becomes high impedance when V_FB3 goes over
110% of its set point.
INTV_CC (Pin 22/Pin 26): Output of the Internal Linear
Low Dropout Regulator. The driver and control circuits
are powered from this voltage source. Must be decoupled
to PGND with a minimum of 4.7µF ceramic or tantalum
capacitor.
EXTV_CC (Pin 23/Pin 27): External Power Input to an Inter-
nal LDO Connected to INTV_CC. This LDO supplies INTV_CC
power, bypassing the internal LDO powered from V_BIAS
whenever EXTV_CC is higher than 4.7V. See EXTV_CC Con-
nection in the Applications Information section. Do not
float or exceed 14V on this pin.
V_BIAS (Pin 24/Pin 28): Main Bias Input Supply Pin. A
bypass capacitor should be tied between this pin and the
SGND pin.
BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High
Current Gate Drives for Bottom (Synchronous) N-Channel
MOSFETs. Voltage swing at these pins is from ground to
INTV_CC.
BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34,
24, 30): Bootstrapped Supplies to the Top Side Floating
Drivers. Capacitors are connected between the BOOST and
SW pins and Schottky diodes are tied between the BOOST
and INTV_CC pins. Voltage swing at the BOOST pins is from
INTV_CC to (V_IN + INTV_CC).
SW1, SW2, SW3 (Pins 31, 19, 28/Pins 35, 23, 32):
Switch Node Connections to Inductors.
TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High
Current Gate Drives for Top N-Channel MOSFETs. These are
the outputs of floating drivers with a voltage swing equal
to INTV_CC superimposed on the switch node voltage SW.
PGOOD1 (Pin 33/Pin 37): Open-Drain Logic Output.
PGOOD1 is pulled to ground when the voltage on the V_FB1
pin is not within ±10% of its set point.
For more information www.linear.com/3859AL
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