LTC3408_15 Datasheet, PDF (10/12 Pages) Linear Technology – 1.5MHz, 600mA Synchronous Step-Down Regulator with Bypass Transistor

LTC3408
APPLICATIO S I FOR ATIO
1
0.1
0.01
0.01
1
100
90
80
70
60
50
40
30
V_OUT = 1.2V
V_OUT = 1.5V
20
V_OUT = 1.8V ₁₀
V_OUT = 2.5V
0
10
100
1000
LOAD CURRENT (mA)
3408 F04
Figure 4. Power Lost vs Load Current
I_GATECHG = f(Q_T + Q_B), where Q_T and Q_B are the gate
charges of the internal top and bottom switches. Both the
DC bias and gate charge losses are proportional to V_IN,
thus, their effects will be more pronounced at higher
supply voltages. (The gate charge of the bypass FET is,
of course, negligible because it is infrequently cycled.)
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In con-
tinuous mode, the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R_DS(ON) and the duty cycle (DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Charateristics
curves. Hence, to obtain I²R losses, simply add R_SW to R_L
and multiply the result by the square of the average output
current.
Other losses including C_IN and C_OUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3408 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3408 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
10
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To prevent the LTC3408 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T_R = (PD)(θ_JA)
where PD is the power dissipated by the regulator and θ_JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider the LTC3408 in dropout at an
input voltage of 2.7V, a load current of 600mA (0.9V ≤ V_REF
< 1.2V) and an ambient temperature of 70°C. With V_REF <
1.2V, the entire 600mA flows through the main P-channel
FET. From the typical performance graph of switch resis-
tance, the R_DS(ON) of the P-channel switch at 70°C is
approximately 0.52Ω. Therefore, power dissipated by the
part is:
PD = (I_LOAD2) • R_DS(ON) = 187.2mW
For the 8L DFN package, the θ_JA is 43°C/W. Thus, the
junction temperature of the regulator is:
T_J = 70°C + (0.1872)(43) = 78°C
which is below the maximum junction temperature of
125°C.
Modifying this example, suppose that V_REF is raised to
1.2V or higher. This turns on the bypass P-channel FET as
well as the main P-channel FET. Assume that the inductor’s
DC resistance is 0.1Ω, the R_DS(ON) of the main P-channel
switch is 0.52Ω, and the R_DS(ON) of the bypass P-channel
switch is 0.08Ω. The current through the P-channel switch
and the inductor will be 69mA, causing power dissipation
of (0.069A)² • 0.62Ω = 2.9mW. The bypass FET will
3408f