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| LTC3407AIDD Datasheet, PDF (3/16 Pages) Linear Integrated Systems – Dual Synchronous, 600mA, 1.5MHz Step-Down DC/DC Regulator | |||
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LTC3407
ELECTRICAL CHARACTERISTICS The l denotes the speciï¬cations which apply over the full operating
temperature range, otherwise speciï¬cations are at TA = 25°C. VIN = 3.6V, unless otherwise speciï¬ed. (Note 2)
SYMBOL
IS
fOSC
fSYNC
ILIM
RDS(ON)
PARAMETER
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
Oscillator Frequency
Synchronization Frequency
Peak Switch Current Limit
Top Switch On-Resistance
Bottom Switch On-Resistance
CONDITIONS
MIN
VFB1 = VFB2 = 0.5V
VFB1 = VFB2 = 0.63V, MODE/SYNC = 3.6V
RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V
VFBX = 0.6V
â 1.2
VIN = 3V, VFB = 0.5V, Duty Cycle <35%
0.75
(Note 6)
(Note 6)
TYP MAX UNITS
600 800
μA
40
60
μA
0.1
1
μA
1.5
1.8
MHz
1.5
MHz
1
1.25
A
0.35 0.45
Ω
0.30 0.45
Ω
ISW(LKG)
POR
Switch Leakage Current
Power-On Reset Threshold
Power-On Reset On-Resistance
VIN = 5V, VRUN = 0V, VFBX = 0V
VFBX Ramping Up, MODE/SYNC = 0V
VFBX Ramping Down, MODE/SYNC = 0V
0.01
1
μA
8.5
%
â8.5
%
100 200
Ω
Power-On Reset Delay
262,144
Cycles
VRUN
IRUN
VMODE
RUN Threshold
RUN Leakage Current
Mode Threshold Low
Mode Threshold High
â 0.3
1
1.5
V
â
0.01
1
μA
0
VIN â 0.5
0.5
V
VIN
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3407E is guaranteed to meet speciï¬ed performance
from 0°C to 70°C. Speciï¬cations over the â 40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3407 is tested in a proprietary test mode that connects VFB
to the output of the error ampliï¬er.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD ⢠θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
SW
5V/DIV
VOUT
100mV/DIV
IL
200mA/DIV
VIN = 3.6V
4μs/DIV
VOUT = 1.8V
ILOAD = 50mA
CIRCUIT OF FIGURE 1
Pulse-Skipping Mode
SW
5V/DIV
VOUT
10mV/DIV
IL
200mA/DIV
3407 G01
VIN = 3.6V
1μs/DIV
VOUT = 1.8V
ILOAD = 50mA
CIRCUIT OF FIGURE 1
Load Step
VOUT
200mV/DIV
IL
500mA/DIV
ILOAD
500mA/DIV
3407 G02
VIN = 3.6V
20μs/DIV
VOUT = 1.8V
ILOAD = 50mA TO 600mA
CIRCUIT OF FIGURE 1
3407 G03
3407fa
3
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