2064VE Datasheet, PDF (9/15 Pages) Lattice Semiconductor – 3.3V In-System Programmable High Density SuperFAST™ PLD

Specifications ispLSI 2064VE
Power Consumption
Power consumption in the ispLSI 2064VE device de- used. Figure 3 shows the relationship between power
pends on two primary factors: the speed at which the and operating speed.
device is operating and the number of Product Terms
Figure 3. Typical Device Power Consumption vs fmax
160
ispLSI 2064VE
140
120
100
80
0
50 100 150 200
fmax (MHz)
Notes: Configuration of four 16-bit counters
Typical current at 3.3V, 25° C
ICC can be estimated for the ispLSI 2064VE using the following equation:
ICC(mA) = 8 + (# of PTs * 0.67) + (# of Nets * Max. Freq. * 0.0045)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
0127/2064VE
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