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2064VE Datasheet, PDF (8/15 Pages) Lattice Semiconductor – 3.3V In-System Programmable High Density SuperFAST™ PLD
ispLSI 2064VE Timing Model
I/O Cell
GRP
Ded. In
I/O Pin
(Input)
#21
I/O Delay
#20
GRP
#22
#45
Reset
Y0,1,2
GOE 0,1
#43, 44
#42
Specifications ispLSI 2064VE
GLB
Feedback
Comb 4 PT Bypass #23
Reg 4 PT Bypass
#24
GLB Reg Bypass
#28
20 PT
XOR Delays
#25, 26, 27
GLB Reg
Delay
D
Q
RST
#29, 30,
31, 32
Control RE
PTs OE
#33, 34, CK
35
ORP
I/O Cell
ORP Bypass
#37
ORP
Delay
#36
#38,
39
I/O Pin
(Output)
#40, 41
0491/2064
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
3.1ns = (0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
2.9ns = (0.5 + 0.6 + 4.0) + (1.8) - (0.5 + 0.6 + 2.9)
tco
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
8.4ns = (0.5 + 0.6 + 4.0) + (0.3) + (1.5 + 1.5)
Note: Calculations are based on timing specifications for the ispLSI 2064VE-200L.
Table 2-0042/2064VE
8