2064VE Datasheet, PDF (12/15 Pages) Lattice Semiconductor – 3.3V In-System Programmable High Density SuperFAST™ PLD

Specifications ispLSI 2064VE
Signal Configuration
ispLSI 2064VE 100-Ball caBGA Signal Diagram
10 9 8 7 6 5 4 3 2 1
A
I/O
I/O
NC¹
I/O
NC¹ VCC
I/O
I/O
I/O
I/O
39
41
46
50
52
55
57
A
B
I/O
37
I/O
40
I/O
43
GND
TDO/
IN 2
I/O
49
I/O
54
I/O
56
I/O
58
I/O
59
B
C
I/O
I/O
I/O
I/O
I/O
I/O
NC¹ NC¹
I/O
I/O
35
38
42
45
47
51
60
61
C
D
I/O
I/O
NC^{1 I/O}
NC¹
I/O
I/O
I/O
RESET
NC¹
32
36
44
53
62
63
D
E
NC¹ NC¹
I/O
NC¹
I/O
BSCAN
I/O
33
48
2
Y0
VCC
GOE
1
E
F
VCC ^GOE Y2
I/O
Y1
I/O
NC¹
I/O
TDI/ _GND
0
34
16
1
IN 0
F
G
TCK/ _GND I/O
I/O
I/O
NC¹
I/O
NC¹
I/O
I/O
IN 3
31
30
21
12
4
0
G
H
I/O
I/O
NC¹ NC¹
I/O
I/O
I/O
I/O
I/O
I/O
29
28
19
15
13
10
6
3
H
J
I/O
27
I/O
26
I/O
24
I/O
22
I/O
17
TMS/
IN 1
VCC
I/O
11
I/O
8
I/O
5
J
K
I/O
I/O
I/O
I/O
GND NC¹
I/O
NC¹
I/O
I/O
25
23
20
18
14
9
7
K
ispLSI 2064VE
Bottom View
10 9 8 7 6 5 4 3 2 1
100-BGA/2064VE
1_{NCs are not to be connected to any active signals, VCC or GND.}
Note: Ball A1 indicator dot on top side of package.
12