2064E Datasheet, PDF (8/11 Pages) Lattice Semiconductor – In-System Programmable SuperFAST™ High Density PLD

Specifications ispLSI 2064E
Power Consumption
Power consumption in the ispLSI 2064E device depends Figure 3 shows the relationship between power and
on two primary factors: the speed at which the device is operating speed.
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
160
150
140
130
120
110
100
90
80
70
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ispLSI 2064E
20 40 60 80 100 120 140 160 180 200
fmax (MHz)
Notes: Configuration of Four 16-bit Counters
Typical Current at 5V, 25° C
ICC can be estimated for the ispLSI 2064E using the following equation:
ICC(mA) = 7 + (# of PTs * 0.75) + (# of nets * Max freq * 0.004)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127A/2064E
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