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2064E Datasheet, PDF (5/11 Pages) Lattice Semiconductor – In-System Programmable SuperFAST™ High Density PLD | |||
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Specifications ispLSI 2064E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
COND.4
#2
DESCRIPTION1
-200
-135
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Prop Delay, 4PT Bypass, ORP Bypass
â 4.5 â 7.5 â 10.0 ns
tpd2
A 2 Data Prop Delay
â 7.0 â 10.0 â 13.0 ns
fmax
A 3 Clk Freq with Internal Feedback3
200 â 135 â 100 â MHz
fmax (Ext.)
fmax (Tog.)
â
4
Clk
Freq
with
External
Feedback
(1
tsu2 +
) tco1
â 5 Clk Frequency, Max. Toggle
133 â 100 â 77 â
200 â 143 â 100 â
MHz
MHz
tsu1
â 6 GLB Reg Setup Time before Clk, 4 PT Bypass 3.5 â 5.0 â 6.5 â ns
tco1
A 7 GLB Reg Clk to Output Delay, ORP Bypass
â 3.0 â 4.0 â 5.0 ns
th1
â
8 GLB Reg Hold Time after Clk, 4 PT Bypass
0.0 â 0.0 â 0.0 â
ns
tsu2
â 9 GLB Reg Setup Time before Clk
4.5 â 6.0 â 8.0 â ns
tco2
â 10 GLB Reg Clk to Output Delay
â 3.5 â 4.5 â 6.0 ns
th2
â 11 GLB Reg Hold Time after Clk
0.0 â 0.0 â 0.0 â ns
tr1
A 12 External Reset Pin to Output Delay
â 6.0 â 10.0 â 13.5 ns
trw1
â 13 External Reset Pulse Duration
3.5 â 5.0 â 6.5 â ns
tptoeen
B 14 Input to Output Enable
â 8.0 â 12.0 â 15.0 ns
tptoedis
C 15 Input to Output Disable
â 8.0 â 12.0 â 15.0 ns
tgoeen
B 16 Global OE Output Enable
â 4.0 â 7.0 â 9.0 ns
tgoedis
C 17 Global OE Output Disable
â 4.0 â 7.0 â 9.0 ns
twh
â 18 External Synch Clk Pulse Duration, High
2.5 â 3.5 â 5.0 â ns
twl
â 19 External Synch Clk Pulse Duration, Low
2.5 â 3.5 â 5.0 â ns
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/2064E
5
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