ISPPAC-POWR1220AT8 Datasheet, PDF (47/54 Pages) Lattice Semiconductor – In-System Programmable Power Supply Monitoring, Sequencing and Margining Controller

Lattice Semiconductor
ispPAC-POWR1220AT8 Data Sheet
ified. Table 1-13 lists the instructions supported by the ispPAC-POWR1220AT8 JTAG Test Access Port (TAP) con-
troller:
Table 1-13. ispPAC-POWR1220AT8 TAP Instruction Table
Instruction
BULK_ERASE
BYPASS
DISCHARGE
ERASE_DONE_BIT
EXTEST
IDCODE
OUTPUTS_HIGHZ
SAMPLE/PRELOAD
PROGRAM_DISABLE
PROGRAM_DONE_BIT
PROGRAM_ENABLE
PROGRAM_SECURITY
RESET
IN1_RESET_JTAG_BIT
IN1_SET_JTAG_BIT
CFG_ADDRESS
CFG_DATA_SHIFT
CFG_ERASE
CFG_PROGRAM
CFG_VERIFY
PLD_ADDRESS_SHIFT
PLD_DATA_SHIFT
PLD_INIT_ADDR_FOR_PROG_INCR
PLD_PROG_INCR
PLD_PROGRAM
PLD_VERIFY
PLD_VERIFY_INCR
UES_PROGRAM
UES_READ
Command
Code
0000 0011
1111 1111
0001 0100
0010 0100
0000 0000
0001 0110
0001 1000
00011100
0001 1110
0010 1111
0001 0101
0000 1001
0010 0010
0001 0010
0001 0011
0010 1011
0010 1101
0010 1001
0010 1110
0010 1000
0000 0001
0000 0010
0010 0001
0010 0111
0000 0111
0000 1010
0010 1010
0001 1010
0001 0111
Comments
Bulk erase device
Bypass - connect TDO to TDI
Fast VPP discharge
Erases ‘Done’ bit only
Bypass - connect TDO to TDI
Read contents of manufacturer ID code (32 bits)
Force all outputs to High-Z state, FET outputs pulled low
Sample/Preload. Default to bypass.
Disable program mode
Programs the Done bit
Enable program mode
Program security fuse
Resets device (refer to the RESETb Signal, RESET Command via
JTAG or I²C section of this data sheet)
Reset the JTAG bit associated with IN1 pin to 0
Set the JTAG bit associated with IN1 pin to 1
Select non-PLD address register
Non-PLD data shift
ERASE Just the Non PLD configuration
Non-PLD program
VRIFY non-PLD fusemap data
PLD_Address register (169 bits)
PLD_Data register (243 Bits)
Initialize the address register for auto increment
Program column register to E² and auto increment address register
Program PLD data register to E²
Verifies PLD column data
Load column register from E² and auto increment address register
Program UES bits into E²
Read contents of UES register from E² (32 bits)
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC-
POWR1220AT8. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC-POWR1220AT8 has no boundary scan register, so for compatibility it defaults to the
BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown
in Table 1-13.
The EXTEST (external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
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