ISPPAC-POWR1220AT8 Datasheet, PDF (35/54 Pages) Lattice Semiconductor – In-System Programmable Power Supply Monitoring, Sequencing and Margining Controller

Lattice Semiconductor
ispPAC-POWR1220AT8 Data Sheet
Table 1-10. ADC Input Attenuator Control
ATTEN (ADC_MUX.4)
0
1
Resolution
2mV
6mV
Full-Scale Range
2.048 V
6.144 V
The input selector may be set to monitor any one of the twelve VMON inputs, the VCCA input, or the VCCINP input.
Table 1-11 shows the codes associated with each input selection.
Table 1-11. V_MON Address Selection Table
SEL3
(ADC_MUX.3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Select Word
SEL2
SEL1
(ADC_MUX.2) (ADC_MUX.1)
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
SEL0
(ADC_MUX.0)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Channel
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
VMON12
VCCA
VCCINP
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-
sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I²C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-
mended that the I²C master load a second conversion command only after the completion of the current conversion
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time
(see T_CONVERT value in the specifications) and disregard checking the DONE bit.
Note that if the I²C clock rate falls below 50kHz (see F_I2C note in specifications), the only way to insure a valid ADC
conversion is to wait the minimum specified time (T_CONVERT), as the operation of the DONE bit at clock rates lower
than that cannot be guaranteed. In other words, if the I²C clock rate is less than 50kHz, the DONE bit may or may
not assert even though a valid conversion result is available.
To insure every ADC conversion result is valid, preferred operation is to clock I²C at more than 50kHz and verify
DONE bit status or wait for the full T_CONVERT time period between subsequent ADC convert commands. If an I²C
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The status of the digital input lines may also be monitored and controlled through I²C commands. Figure 1-26
shows the I²C interface to the IN[1:6] digital input lines. The input status may be monitored by reading the
INPUT_STATUS register, while input values to the PLD array may be set by writing to the INPUT_VALUE register.
To be able to set an input value for the PLD array, the input multiplexer associated with that bit needs to be set to
the I²C register setting in E²CMOS memory otherwise the PLD will receive its input from the INx pin.
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