ISPGDX160VVA Datasheet, PDF (24/36 Pages) Lattice Semiconductor – ispGDX®160V/VA Device Datasheet

Specifications ispGDX160V/VA
Boundary Scan
The ispGDXV/VA devices provide IEEE1149.1a test allows customers using boundary scan test to have full
capability and ISP programming through a standard test capability with only a single BSDL file.
Boundary Scan Test Access Port (TAP) interface.
The ispGDXV/VA devices are identified by the 32-bit
The boundary scan circuitry on the ispGDXV/VA Family JTAG IDCODE register. The device ID assignments are
operates independently of the programmed pattern. This listed in Table 4.
S _{Figure 10. Boundary Scan Register Circuit for I/O Pins}
ICE ^SCANIN
(from previous
DEVINUED ^cell
BSCAN
Registers
DQ
DQ
BSCAN
Latches
DQ
EXTEST
HIGHZ
TOE
Normal
Function ⁰
OE ₁
EXTEST
PROG_MODE
DQ
Normal
Function
0
1
I/O Pin
CT _{NT D Q}
SCANOUT
(to next cell)
ELE ^{CO ShiftDR}
Clock DR
Update DR
Reset
S ^{IS Table 3. I/O Shift Register Order}
DEVICE
D ^{ispGDX160V/VA}
I/O SHIFT REGISTER ORDER
TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, I/O B19 .. B0,
I/O A39.. A0, I/O D39 .. D20, TDO
I/O Shift Reg Order/ispGDXVA
Table 4. ispGDX160V/VA Device ID Codes
DEVICE
ispGDX160V
ispGDX160VA
32-BIT BOUNDARY SCAN ID CODE
0000, 0000, 0011, 0101, 0011, 0000, 0100, 0011
0001, 0000, 0011, 0101, 0011, 0000, 0100, 0011
ID Code/GDX160V/VA
23