ISPGDX160VVA Datasheet, PDF (14/36 Pages) Lattice Semiconductor – ispGDX®160V/VA Device Datasheet

Specifications ispGDX160VA
External Timing Parameters (Continued)
ispGDX160VA timings are specified with a GRP load apply to any signal path traversing the GRP (MUXA-D,
(fanout) of four I/O cells. The figure below shows the ∆ OE, CLK/CLKEN, MUXsel0-1). Global Clock signals
GRP Delay with increased GRP loads. These deltas which do not use the GRP have no fanout delay adder.
ispGDX160VA Maximum ∆ GRP Delay vs. I/O Cell Fanout
S 1.6
1.4
E _1.2
1.0
IC ^0.8
D ^0.6
0.4
V _{E 0.2}
0.0
E ^{0 4 10 20 30 40 50 60 70}
SELDEICSTCODNTINU ^{I/OCellFanout}
13