ISPGDX160VVA Datasheet, PDF (21/36 Pages) Lattice Semiconductor – ispGDX®160V/VA Device Datasheet

Specifications ispGDX160V
Internal Timing Parameters¹
Over Recommended Operating Conditions
-5
-7
PARAMETER #
DESCRIPTION¹
MIN. MAX. MIN. MAX. UNITS
Inputs
t_io
GRP
S t_grp
MUX
t_muxd
E _tmuxexp
t_muxs
IC ^tmuxsio
t_muxsg
D _tmuxselexp
Register
V _{E tiolat}
t_iosu
E ^tioh
U _tioco
t_ior
D tcesu
IN ^tceh
Data Path
t_fdbk
T _{T tiobp}
t_ioob
C ^tmuxcg
N _tmuxcio
t_iodg
E _tiodio
O _Outputs
L t_ob
E ^{C tobs}
t_oeen
t_oedis
S ^{IS tgoe}
t_toe
Clocks
D ^tioclk
32 Input Buffer Delay
33 GRP Delay
34 I/O Cell MUX A/B/C/D Data Delay
35 I/O Cell MUX A/B/C/D Expander Delay
36 I/O Cell Data Select
37 I/O Cell Data Select (I/O Clk)
38 I/O Cell Data Select (Yx Clk)
39 I/O Cell MUX Data Select Expander Delay
40 I/O Latch Delay
41 I/O Register Setup Time Before Clock
42 I/O Register Hold Time After Clock
43 I/O Register Clock to Output Delay
44 I/O Reset to Output Delay
45 I/O Clock Enable Setup Time Before Clock
46 I/O Clock Enable Hold Time After Clock
47 I/O Register Feedback Delay
48 I/O Register Bypass Delay
49 I/O Register Output Buffer Delay
50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clk)
51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clk)
52 I/O Register I/O MUX Delay (Yx Clk)
53 I/O Register I/O MUX Delay (I/O Clk)
54 Output Buffer Delay
55 Output Buffer Delay (Slow Slew Option)
56 I/O Cell OE to Output Enable
57 I/O Cell OE to Output Disable
58 GRP Output Enable and Disable Delay
59 Test OE Enable and Disable Delay
60 I/O Clock Delay
— 0.9 — 1.4 ns
— 1.1 — 1.1 ns
— 1.5 — 2.0 ns
— 2.0 — 2.5 ns
— 3.0 — 4.0 ns
— 4.5 — 6.5 ns
— 3.5 — 4.5 ns
— 3.5 — 4.5 ns
— 1.0 — 1.0 ns
— 2.0 — 3.2 ns
— 1.5 — 2.3 ns
— 0.5 — 0.5 ns
— 1.5 — 1.5 ns
— 2.0 — 2.5 ns
— 0.5 — 1.0 ns
— 0.9 — 1.2 ns
— 0.0 — 0.3 ns
— 0.0 — 0.6 ns
— 2.0 — 2.5 ns
— 3.0 — 4.5 ns
— 4.0 — 5.0 ns
— 5.0 — 7.0 ns
— 1.5 — 2.2 ns
— 9.5 — 14.2 ns
— 4.0 — 6.0 ns
— 4.0 — 6.0 ns
— 0.0 — 0.0 ns
— 5.0 — 6.0 ns
— 2.0 — 3.2 ns
t_gclk
61 Global Clock Delay
— 2.0 — 2.7 ns
t_gclkeng
62 Global Clock Enable (Yx Clk)
— 2.5 — 3.7 ns
t_gclkenio
63 Global Clock Enable (I/O Clk)
— 3.5 — 5.7 ns
t_ioclkeng
64 I/O Clock Enable (Yx Clk)
— 2.5 — 4.2 ns
Global Reset
t_gr
65 Global Reset to I/O Register Latch
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
— 11.0 — 13.7 ns
20