ISPGDX2 Datasheet, PDF (18/72 Pages) Lattice Semiconductor – High Performance Interfacing and Switching

Lattice Semiconductor
Figure 14. sysHSI Block with SERDES and FIFO
sysHSI Block
SERDES
SOUT
Serializer
TXD
10
RXD
10
SIN
De-serializer
including CDR ^RECCLK
CSLOCK
SS_CLKOUT
SS_CLKIN
CAL
CSPLL
CSLOCK
ispGDX2 Family Data Sheet
Core Logic
FIFO
GDX
Block
GRP
Shared Source Synchronous
pins drive multiple sysHSI
blocks
SERDES
SOUT
Serializer
TXD
10
RXD
10
SIN
De-serializer
including CDR ^RECCLK
FIFO
GDX
Block
REFCLK (0:3)
Reference clocks
from CLK (0:3)
Note: Some pins are shared. See Logic Signal Connections table for details
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