|
ISPGDX2 Datasheet, PDF (1/72 Pages) Lattice Semiconductor – High Performance Interfacing and Switching | |||
|
ispGDX2⢠Family
Includes
High-
High Performance Interfacing and Switching
September 2005
Features
Performance,
Low-Cost
âE-Seriesâ â Two Options Available
Data Sheet
⢠High-performance sysHSI (standard part number)
â High Performance Bus Switching
⢠Low-cost, no sysHSI (âE-Seriesâ)
⢠High bandwidth
â Up to 12.8 Gbps (SERDES)
â sysHSI Blocks Provide up to 16 High-speed
â Up to 38 Gbps (without SERDES)
Channels
⢠Up to 16 (15x10) FIFOs for data buffering
⢠Serializer/de-serializer (SERDES) included
⢠High speed performance
⢠Clock Data Recovery (CDR) built in
â fMAX = 360MHz
â tPD = 3.0ns
â tCO = 2.9ns
â tS = 2.0ns
⢠Built-in programmable control logic capability
⢠800 Mbps per channel
⢠LVDS differential support
⢠10B/12B support
â Encoding / decoding
â Bit alignment
⢠I/O intensive: 64 to 256 I/Os
â Symbol alignment
⢠Expanded MUX capability up to 188:1 MUX
⢠8B/10B support
â Bit alignment
â sysCLOCK⢠PLL
â Symbol alignment
⢠Frequency synthesis and skew management
⢠Source Synchronous support
⢠Clock multiply and divide capability
⢠Clock shifting up to +/-2.35ns in 335ps steps
â Flexible Programming and Testing
⢠Up to four PLLs
⢠IEEE 1532 compliant In-System Programmabil-
ity (ISPâ¢)
â sysIO⢠Interfacing
⢠Boundary scan test through IEEE 1149.1
⢠LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
interface
standard board interfaces
⢠3.3V, 2.5V or 1.8V power supplies
⢠SSTL 2/3 Class I and II support
⢠5V tolerant I/O for LVCMOS 3.3 and LVTTL
⢠HSTL Class I, III and IV support
interfaces
⢠GTL+, PCI-X for bus interfaces
⢠LVPECL, LVDS and Bus LVDS differential support
⢠Hot socketing
⢠Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os
64
128
256
GDX Blocks
4
8
16
tPD
tS
tCO
fMAX (Toggle)
Max Bandwidth
sysHSI Channels2
SERDES1, 2
Without SERDES3
3.0ns
2.0ns
2.9ns
360MHz
3.2Gbps
11Gbps
4
3.2ns
2.0ns
3.1ns
330MHz
6.4Gbps
21Gbps
8
3.5ns
2.0ns
3.2ns
300MHz
12.8Gbps
38Gbps
16
LVDS/Bus LVDS (Pairs)
32
64
128
PLLs
2
2
4
Package
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. âE-Seriesâ does not support sysHSI.
3. fMAX (Toggle) * maximum I/Os divided by 2.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speciï¬cations and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13
|
▷ |