1024EA Datasheet, PDF (10/13 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Maximum GRP Delay vs GLB Loads
4
3
2
Specifications ispLSI 1024EA
ispLSI 1024EA-100
ispLSI 1024EA-125
ispLSI 1024EA-200
1
14
8 16
GLB Load
24
GRP/GLB/1024EA
Power Consumption
Power consumption in the ispLSI 1024EA device de- used. Figure 4 shows the relationship between power
pends on two primary factors: the speed at which the and operating speed.
device is operating, and the number of product terms
Figure 4. Typical Device Power Consumption vs fmax
260
240
ispLSI 1024EA
220
200
180
160
140
120
100
0
50 100 150 200 250
fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
Icc can be estimated for the ispLSI 1024EA using the following equation:
Icc = 17mA + (# of PTs * .726) + (# of nets * Max Freq * .0043)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
0127/1024EA
10