U4305B Datasheet, PDF (17/20 Pages) Keysight Technologies – Protocol Exerciser for PCI Express® 3.0

17 | Keysight | U4305B Protocol Exerciser for PCI Express^® 3.0 - Data Sheet
N5316A PCIe Gen2/Gen3 Test Backplane
General
Power
Link width
Clocks
Connectors
Provides power and clock to DUT
Test fixture for add-in card testing with exerciser
Separate power on/off for fast reset in tests
Power reset
AUX (stand by) power for add-in card available if required
Per bus power switch
All link widths are supported
Clock generation with/without SSC
Input for external clock
Clock output (e.g. for oscilloscope measurements)
Supports different mid-bus probes N4241A/2A/3A
Reset/power button
Bus 1
–– One pair of x16 PCIe connectors
–– Two x8 mid-bus probe retention modules with bidirectional footprint supporting N4242A (x16), N4241A (x1, x4, x8),
N4243A (dual x4)
Bus 2
–– One x16 PCIe connector with loop back
Bus 3
–– One pair of x16 PCIe connectors
–– Two x8 mid-bus probe retention modules with unidirectional footprint supporting two N4241A (x1, x4, x8, x16)
Figure 14.