8T49N282_16 Datasheet, PDF (65/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N282 Datasheet
Power Dissipation and Thermal Considerations
The 8T49N282 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is
highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions
is enabled.
The 8T49N282 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.
The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the
power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your
own specific configuration.
Power Domains
The 8T49N282 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all
power supply pins must still be connected to a valid supply voltage). Figure 16 below indicates the individual domains and the associated power
pins.
CLK Input &
Divider Block
(Core V_CC)
Analog & Digital PLL0
(V_CCA and Core V_CC)
Analog & Digital PLL1
(V_CCA and Core V_CC)
Output Divider / Buffer Q0 (VCCO0)
Output Divider / Buffer Q1 (VCCO1)
Output Divider / Buffer Q2 (VCCO2)
Output Divider / Buffer Q3 (V_CCO3)
Output Divider / Buffer Q4 (V_CCO4)
Output Divider / Buffer Q5 (VCCO5)
Output Divider / Buffer Q6 (VCCO6)
Output Divider / Buffer Q7 (VCCO7)
Figure 16. 8T49N282 Power Domains
For the output paths shown above, there are three different structures that are used. Q0 and Q1 use one output path structure, Q2 and Q3 use
a second structure and Q4 – Q7 use a 3^rd structure. Power consumption data will vary slightly depending on the structure used as shown in
the appropriate tables below.
Power Consumption Calculation
Determining total power consumption involves several steps:
1. Determine the power consumption using maximum current values for core and analog voltage supplies from Tables 8A and 8B.
2. Determine the nominal power consumption of each enabled output path.
a. This consists of a base amount of power that is independent of operating frequency, as shown in Tables 17A through 17G
(depending on the chosen output protocol).
b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output
frequency by the FQ_Factor shown in Tables 17A through 17G.
3. All of the above totals are then summed.
©2016 Integrated Device Technology, Inc.
65
Revision H, October 26, 2016