8T49N282_16 Datasheet, PDF (28/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N282 Datasheet
Bit Field Name
PLLGAIN1[1:0]
TGLCKBW1[2:0]
TGLCKDMP1[2:0]
TGLCKHYS1
TGLCKTHR1[6:0]
SLEW1[1:0]
HOLD1[1:0]
HOLDAVG1
FASTLCK1
LOCK1[7:0]
Digital PLL1 Feedback Configuration Register Block Field Descriptions
Field Type Default Value Description
Digital Loop Filter Gain Settings for Digital PLL1:
00 = 0.5
R/W
01b
01 = 1.0
10 = 1.5
11 = 2.0
Loop Bandwidth Setting used when PLL1 is in tight lock and phase error is very
close to 0:
000 = Off (Use Locked loop bandwidth LCKBW1[3:0])
001 = 1Hz
R/W
011b
010 = 2Hz
011 = 4Hz
100 = 8Hz
101 = 16Hz
110 = 32Hz
111 = 64Hz
Tight Lock Operation Damping Factor for PLL1:
000 = Off (Use Locked Damping Factor LCKDAMP1[2:0])
001 = 1
010 = 2
R/W
000b
011 = 5
100 = 10
101 = 20
110 = Reserved
111 = Reserved
Tight Lock Hysteresis Enable for PLL1. Indicates when Tight Lock Operation is
entered / exited.
R/W
0b
0 = Non-hysteresis - enter & exit when phase error crosses threshold in
TGLCKTHR1[6:0]
1 = Hysteresis - enter when phase error less than 5nsec and exit when larger than
TGLCKTHR1[6:0]
Tight Lock Threshold for PLL1, used to decide when to enter / exit Tight Lock
R/W
00h
operation.
Effective value = (entered value + 2) * (PLL0 period * 8 = 2.0-2.67nsec). Range is
4-345nsec.
Phase-slope control for Digital PLL1:
00 = no limit - controlled by loop bandwidth of Digital PLL1, NOTE 1.
R/W
00b
01 = 193µsec/sec
10 = 24µsec/sec
11 = Reserved
Holdover Averaging mode selection for Digital PLL1:
00 = Instantaneous mode - uses historical value 100ms prior to entering holdover
R/W
00b
01 = Fast Average Mode
10 = Reserved
11 = Set VCO control voltage to V_CC/2
Holdover Averaging Enable for Digital PLL1:
R/W
0b
0 = Holdover averaging disabled
1 = Holdover averaging enabled as defined in HOLD1[1:0]
Enables Fast Lock operation for Digital PLL1:
R/W
0b
0 = Normal locking using LCKBW1 & LCKDAMP1 fields in all cases
1 = Fast Lock mode using ACQBW1 & ACQDAMP1 when not phase locked and
LCKBW1 & LCKDAMP1 once phase locked
R/W
3Fh
Lock window size for Digital PLL1. Unsigned 2’s complement binary number in
steps of 2.5ns, giving a total range of 640ns. Do not program to 0.
©2016 Integrated Device Technology, Inc.
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Revision H, October 26, 2016