8T49N282_16 Datasheet, PDF (39/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N282 Datasheet
Table 7O. Analog PLL1 Control Register Bit Field Locations and Descriptions
Please contact IDT through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular
user configuration.
Address (Hex)
00B0
00B1
00B2
00B3
Analog PLL1 Control Register Block Field Locations
D7
D6
D5
D4
D3
D2
D1
CPSET_1[2:0]
RS_1[1:0]
CP_1[1:0]
Rsvd
SYN_MODE
1
Rsvd
DLCNT_1
Rsvd
VCOMAN_1
DBIT1_1[4:0]
Rsvd
DBIT2_1[4:0]
D0
WPOST_1
DBITM_1
Bit Field Name
CPSET_1[2:0]
RS_1[1:0]
CP_1[1:0]
WPOST_1
DLCNT_1
DBITM_1
VCOMAN_1
DBIT1_1[4:0]
DBIT2_1[4:0]
SYN_MODE1
Rsvd
Field Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Analog PLL1 Control Register Block Field Descriptions
Default Value Description
100b
Charge Pump Current Setting for Analog PLL1:
000 = 110 µA
001 = 220 µA
010 = 330 µA
011 = 440 µA
100 = 550 µA
101 = 660 µA
110 = 770 µA
111 = 880 µA
Internal Loop Filter Series Resistor Setting for Analog PLL1:
00 = 330 
01b
01 = 640 
10 = 1.2 k
11 = 1.79 k
Internal Loop Filter Parallel Capacitor Setting for Analog PLL1:
00 - 40 pF
01b
01 = 80 pF
10 = 140 pF
11 = 200 pF
Internal Loop Filter 2nd Pole Setting for Analog PLL1:
1b
0 = Rpost = 497 , Cpost = 40pF
1 = Rpost = 1.58 k, Cpost = 40pF
Digital Lock Count Setting for Analog PLL1: Set to 0 if external capacitor (CAP1)
1b
for PLL1 is >95nF, otherwise set to 1:
0 = 1 ppm accuracy
1 = 16 ppm accuracy
Digital Lock Manual Override Setting for Analog PLL1:
0b
0 = Automatic Mode
1 = Manual Mode
Manual Lock Mode VCO Selection Setting for Analog PLL1:
1b
0 = VCO2
1 = VCO1
01011b
Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL1:
00000b
Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL1.
Frequency Synthesizer Mode Control for PLL1:
0 = PLL1 jitter attenuates and translates one or more input references.
0b
1 = PLL1 synthesizes output frequencies using only the crystal as a reference.
Note that the STATE1[1:0] field in the Digital PLL1 Control Register must be set to
Force Freerun state.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2016 Integrated Device Technology, Inc.
39
Revision H, October 26, 2016