CPC5002 Datasheet, PDF (9/14 Pages) IXYS Corporation – Dual High-Speed Open-Drain

INTEGRATED CIRCUITS DIVISION
3.3 Output Drivers
Designed specifically for data and clock busses, the
output drivers have been configured for optimal
performance and behavior.
To reduce RF emissions and ringing on the output
lines the active low output drivers are slew limited. In
addition to limiting emissions, the slew limited outputs
reduce the need for external output series resistors.
Whenever the outputs are in the deasserted logic high
state, the open-drain outputs exhibit low leakage
performance while presenting a high impedance
(Hi-Z) to the load. Additionally, during power-up and
with the loss of V_DD, the outputs default to the Hi-Z
deasserted state thereby ensuring signal integrity of
any bussed, open-drain signals connected to the
output pins
To maximize system design flexibility, the outputs are
tolerant of pull-up voltages greater than the CPC5002
supply voltage, V_DD, provided the pull-up voltage
remains within the output’s specified voltage limits. For
example, using a 3.3V supply to power the CPC5002,
it’s outputs may be safely operated into a pull up
resistor to a supply voltage of 6.5V.
3.4 Power Supply Decoupling and Noise
Reduction
There are no special power supply decoupling
requirements for the CPC5002.
In addition, since the CPC5002 uses optical coupling
to transfer information across the barrier, no internal
clocking circuits are utilized to maintain the proper
output state. This negates the need to implement the
required special layout or noise reduction techniques
necessary to maintain EMI or RFI compliance.
CPC5002
4 Circuit Examples
4.1 Inverting and Non-Inverting Configurations
Shown below are typical inverting and non-inverting
circuit examples with the optional feed forward
capacitors used for high speed signals.
These designs assume a combined voltage drop of
3.3V across the input resistor and the LED with a
nominal input current of 1.5mA.
Figure 1. Inverting Configuration
C_FWD
10pF
V_IN
1.4k
3.3V
1/2 CPC5002
R_PU
499Ω
V_OUT
C_L
20pF
Inverting: V_IN to V_OUT
C_FWD increases instantaneous I_F at LED turn-on to
reduce t_PHL at V_OUT .
Figure 2. Non-Inverting Configuration
V+
1.4k
V_IN
C_FWD
10pF
1/2 CPC5002
3.3V
R_PU
499Ω
V_OUT
C_L
20pF
Non-Inverting: V_IN to V_OUT
For applications where the nominal total voltage drop
across the input resistor and the LED is not 3.3V it will
be necessary to adjust the input resistor’s value.
Examples of this would be different pull-up voltage
supplies and V_IN sources that do not drive completely
to the supply rails.
R01
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