CPC5002 Datasheet, PDF (5/14 Pages) IXYS Corporation – Dual High-Speed Open-Drain

INTEGRATED CIRCUITS DIVISION
CPC5002
1.9 Switching Specifications
Parameter
Timing Specifications
Clock Frequency
Propagation Delay
Output Falling ^{1, 3}
Output Rising ^{2, 3}
Pulse Width Distortion: |t_PLH - t_PLH|
Propagation Delay Skew ³
Output Fall Time, 90% to 10%
Conditions
I_SINK=6mA, C_L=20pF
I_F=1.5mA, V_DD=3.3V,
R_PU=499, C_L=20pF,
0.5V_IN to 0.5V_{DD_OUT}
As per t_PHL and t_PLH
As per t_PHL and t_PLH
I_F=1.5mA, V_DD=3.3V,
R_PU=499, C_L=20pF
Symbol Min Typ Max Units
f_MAX
-
10
-
MHz
t_PHL
35
81
120
ns
t_PLH
35
81
120
PWD
85
ns
t_PSK
-
-
50
ns
t_f
10
15
-
ns
Common Mode Specifications
Common Mode Transient Immunity
V_OUT = High
V_OUT = Low
V_CM=20V_P-P , V_DD=3.3V, T_A=25°C
V_OUT>2V
V_OUT<0.8V
CM_H
5
-
-
CM_L
7
-
kV/s
-
1 _{Falling propagation delay can be reduced by increasing instantaneous LED current drive, typically by increasing CFWD .}
2 _{Rising propagation delay depends on RPU , CL , and IF .}
Increasing I_F above 2 • I_TH (by reducing R_S) increases the rising propagation delay.
3 _{Propagation Delay Skew is the worst case difference propagation delay, High to Low and Low to High between the two channels of a CPC5002}
when measured using the test circuit shown below, which is tuned for approximately even rising and falling delays.
1.10 Propagation Delay Test Circuit
27pF
2kΩ
I_F
½ CPC5002
V_DD
3.3V
V_OUT
R_PU
499Ω
C_L
20pF
R01
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