CPC7593 Datasheet, PDF (12/24 Pages) Clare, Inc. – Line Card Access Switch

INTEGRATED CIRCUITS DIVISION
CPC7593
1.7 Digital I/O Electrical Specifications
Parameter
Test Conditions
Symbol Minimum Typical Maximum
Unit
Input Characteristics
Input voltage, Logic low
Input voltage, Logic high
Input voltage falling
Input voltage rising
V_IL
0.8
1.1
-
V
V_IH
-
1.7
2.0
Input leakage current,
IN_RINGING, IN_TESTin, V_DD = 5.5 V, V_BAT = -75 V, V_IH = 2.4V
I_IH
-
0.1
1
A
and IN_TESTout Logic high
Input leakage current,
IN_RINGING, IN_TESTin, V_DD = 5.5 V, V_BAT = -75 V, V_IL = 0.4V
I_IL
-
0.1
1
A
and IN_TESTout Logic low
Input leakage current,
LATCH Logic high
V_DD = 4.5 V, V_BAT = -75 V, V_IH = 2.4V
I_IH
7
19
-
A
LATCH Pull-up
Minimum Load
V_DD = 4.5 V, V_BAT = -75 V, I_IN = -10 A _{Logic = High}
True
Latch input transitions to logic high.
Input leakage current,
LATCH Logic low
V_DD = 5.5 V, V_BAT = -75 V, V_IL = 0.4V
I_IL
-
47
125
A
Input leakage current,
T_SD Logic high
V_DD = 5.5 V, V_BAT = -75 V, V_IH = V_DD
I_IH
10
16
30
A
Input leakage current,
T_SD Logic low
V_DD = 5.5 V, V_BAT = -75 V, V_IL = 0.4V
I_IL
10
16
30
A
Output Characteristics
Output voltage,
T_SD Logic high
V_DD = 5.5 V, V_BAT = -75 V, I_TSD = A V_{TSD_off}
2.4
V_DD
-
V
Output voltage,
T_SD Logic low
V_DD = 5.5 V, V_BAT = -75 V, I_TSD = mA V_{TSD_on}
-
0
0.4
V
12
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