IS43LD16320A Datasheet, PDF (99/143 Pages) Integrated Silicon Solution, Inc – Four-bit Pre-fetch DDR Architecture

IS43/46LD16320A
IS43/46LD32160A
18. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a
contiguous sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature
drift in the system is <10C/s. Values do not include clock jitter.
19. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a
1.6us rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is <10C/s. Values do
not include clock jitter.
20. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 32ms
rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is <10C/s. Values do not
include clock jitter
Command Input Setup and Hold Timing
T0
T1
T2
T3
CK#
CK
t_IS t_IH
t_IS t_{IH VIH(DC)}
CS#
V _IL(AC)
V _IL(DC)
t_IS t_IH
V _IH(AC)
t_IS t_IH
CA[9:0]
CA
CA
rise
fall
CA
CA
CA
rise
fall
rise
CA
CA
CA
fall
rise
fall
CMD
NOP
Command
NOP
Command
Transitioning data
Don’t Care
Notes:
1. The setup and hold timing shown applies to all commands.
2. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the CKE pin, see Power-Down .
Integrated Silicon Solution, Inc. — www.issi.com
99
Rev. 00C
8/11/2014