IS43LD16320A Datasheet, PDF (9/143 Pages) Integrated Silicon Solution, Inc – Four-bit Pre-fetch DDR Architecture

IS43/46LD16320A
IS43/46LD32160A
FUNCTIONAL DESCRIPTION
LPDDR2-S4 is a high-speed SDRAM device internally configured as an 4-Bank memory. This device contains
536,870,912 bits (512 Megabit)
All LPDDR2 devices use a double data rate archiecture on the Command/Address (CA) bus to reduce the number
of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each
command uses one clock cycle, during which command information is transferred on both the positive and negative
edge of the clock.
This LPDDR2-S4 device also uses a double data rate architecture on the DQ pins to achieve high speed operation.
The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two
data bits per DQ every clock cycle at the I/O pins. A single read or write access for the memory device effectively
consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM core and four corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command.
The address and BA bits registered coincident with the Activate command are used to select the row and the Bank
to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank
and the starting column location for the burst access.
Prior to normal operation, the LPDDR2 must be initialized. The following section provides detailed information cover-
ing device initialization, register definition, command description and device operation.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. 00C
8/11/2014