IS63WV1024BLL Datasheet, PDF (9/17 Pages) Integrated Silicon Solution, Inc – 128K x 8 HIGH-SPEED CMOS STATIC RAM

IS63WV1024BLL
IS64WV1024BLL
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
Parameter
-12 ns
-15 ns
Min. Max.
Min. Max.
Unit
tWC
Write Cycle Time
12
—
15
—
ns
tSCE
CE to Write End
9
—
10
—
ns
tAW
Address Setup Time to
9
—
10
—
ns
Write End
tHA
Address Hold from
Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWE₁₍₁₎
WE Pulse Width (OE High)
9
—
10
—
ns
tPWE₂₍₂₎
WE Pulse Width (OE Low)
11
—
12
—
ns
tSD
Data Setup to Write End
9
—
9
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE⁽²⁾
WE LOW to High-Z Output
—
6
—
7
ns
tLZWE⁽²⁾
WE HIGH to Low-Z Output
3
—
3
—
ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the loading specified in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1^(1,2 (CE Controlled, OE = HIGH or LOW)
ADDRESS
CE
WE
DOUT
DIN
t SA
t WC
VALID ADDRESS
t SCE
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
05/10/06
CE_WR1.eps
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