IS62WV25616DBLL-45TLI Datasheet, PDF (9/17 Pages) Integrated Silicon Solution, Inc – 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM

IS62WV25616DALL/DBLL, IS65WV25616DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
35 ns
45 ns
55 ns
Min. Max.
Min. Max.
Min. Max.
Unit
twc
Write Cycle Time
35 —
45 —
55 —
ns
tscs1/tscs2 CS1/CS2 to Write End
25 —
35 —
45 —
ns
taw
Address Setup Time to Write End 25 —
35 —
45 —
ns
tha
Address Hold from Write End
0 —
0 —
0
—
ns
tsa
Address Setup Time
0 —
0—
0
—
ns
tpwb
LB, UB Valid to End of Write
25 —
35 —
45 —
ns
tpwe
WE Pulse Width
25 —
35 —
40 —
ns
tsd
Data Setup to Write End
20 —
20 —
25 —
ns
thd
Data Hold from Write End
0—
0—
0
—
ns
thzwe⁽³⁾
WE LOW to High-Z Output
— 10
— 20
— 20
ns
tlzwe⁽³⁾
WE HIGH to Low-Z Output
3—
5—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. D
06/19/2013