IS62WV25616DBLL-45TLI Datasheet, PDF (3/17 Pages) Integrated Silicon Solution, Inc – 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM

IS62WV25616DALL/DBLL, IS65WV25616DBLL
TRUTH TABLE

I/O PIN
Mode
WE CS1 CS2 OE LB UB
I/O0-I/O7 I/O8-I/O15 Vdd Current
Not Selected
XHXXXX
X
X
L
X
X
X
XXXXHH
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Isb1, Isb2
Isb1, Isb2
Isb1, Isb2
Output Disabled
H
L
H
H
L
X
H
L
H
H
X
L
High-Z
High-Z
Icc
High-Z
High-Z
Icc
Read

H
L
H
L
L
H
Dout
High-Z Icc
H
L
H
L
H
L
High-Z
Dout
H
L
H
L
L
L Dout Dout
Write

L
L
H
X
L
H
Din
High-Z Icc
L
L
H
X
H
L
High-Z
Din
L
L
H
X
L
L Din Din
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Symbol Parameter
Value
Unit
Vterm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V
Vdd
Vdd Relates to GND
–0.3 to 4.0
V
Tstg
Storage Temperature
–65 to +150
°C
Pt
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE^(1,2)
Symbol Parameter
Conditions
Max.
Cin
Input Capacitance
Vin = 0V
6
C_I/O
Input/Output Capacitance
Vout = 0V
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Unit
pF
pF
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. D
06/19/2013