IS61WV2568EDBLL Datasheet, PDF (9/14 Pages) Integrated Silicon Solution, Inc – 256K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV2568EDBLL
WRITE CYCLE NO. 2^(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
1
t HA
OE
2
CE ^LOW
t AW
3
t PWE1
WE
t SA
t HZWE
t LZWE
4
DOUT
DATA UNDEFINED
HIGH-Z
t SD
t HD
5
DIN
DATAIN VALID
Notes:
CE_WR2.eps
6
1. The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > Vih.
7
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
8
ADDRESS
VALID ADDRESS
OE ^LOW
t HA
9
CE _LOW
WE
DOUT
t SA
DATA UNDEFINED
DIN
t AW
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
10
11
12
CE_WR3.eps
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. A
11/08/2011