IS61WV2568EDBLL Datasheet, PDF (7/14 Pages) Integrated Silicon Solution, Inc – 256K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV2568EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
-8 -10 -20
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Symbol Parameter Min. Max. Min. Max.
Min. Max.
Unit
twc
Write Cycle Time
8—
10 —
20 —
ns
tsce
CE to Write End
6.5 —
8—
12 —
ns
2
taw
Address Setup Time
6.5 —
8—
12 —
ns
to Write End
tha
Address Hold from Write End
0—
0—
0—
ns
tsa
Address Setup Time
0—
0—
0—
ns
3
tpwe1
WE Pulse Width
6.5 —
8—
12 —
ns
tpwe2
WE Pulse Width(OE = LOW)
8.0 —
10 —
17 —
ns
tsd
Data Setup to Write End
5—
6—
9—
ns
4
thd
Data Hold from Write End
0—
0—
0—
­ns
thzwe⁽²⁾ WE LOW to High-Z Output
— 3.5
—5
—9
ns
tlzwe⁽²⁾ WE HIGH to Low-Z Output
2—
2—
2—
ns
5
Notes:
1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW, and WE LOW.All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the rising
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or falling edge of the signal that terminates the write. Shaded area product in development
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10
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Integrated Silicon Solution, Inc. — www.issi.com
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Rev. A
11/08/2011