IS61WV25616ALL Datasheet, PDF (9/21 Pages) Integrated Silicon Solution, Inc – 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
-8
-10
1
Symbol
Parameter
Min. Max.
Min. Max.
Unit
tRC
Read Cycle Time
8—
10 —
ns
tAA
Address Access Time
—8
— 10
ns
2
tOHA
Output Hold Time
2.0 —
2.0 —
ns
tACE
CE Access Time
—8
— 10
ns
tDOE
tHZOE⁽²⁾
OE Access Time
OE to High-Z Output
— 4.5
—3
— 4.5
ns
—4
ns
3
tLZOE⁽²⁾
OE to Low-Z Output
0—
0—
ns
tHZCE⁽²
tLZCE⁽²⁾
CE to High-Z Output
CE to Low-Z Output
03
3—
04
ns
3—
ns
4
tBA
LB, UB Access Time
— 5.5
— 6.5
ns
tHZB⁽²⁾
tLZB⁽²⁾
LB, UB to High-Z Output
LB, UB to Low-Z Output
03
0—
03
ns
0—
ns
5
tPU
Power Up Time
0—
0—
ns
tPD
Notes:
Power Down Time
—8
— 10
ns
6
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. G
07/15/2010