IS63WV1288DALL Datasheet, PDF (8/20 Pages) Integrated Silicon Solution, Inc – 128K x 8 HIGH-SPEED CMOS STATIC RAM

IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)

Symbol Parameter
trc
Read Cycle Time
taa
Address Access Time
toha
Output Hold Time
tace
CE Access Time
tdoe
OE Access Time
tlzoe⁽²⁾
OE to Low-Z Output
thzoe⁽²⁾ OE to High-Z Output
tlzce⁽²⁾
CE to Low-Z Output
thzce⁽²⁾
CE to High-Z Output
tpu
CE to Power Up Time
tpd
CE to Power Down Time
-8 ns
-10 ns
-12 ns
Min. Max.
Min. Max.
Min. Max.
Unit
8
—
10
—
12
—
ns
—
8
—
10
—
12
ns
2
—
2
—
2
—
ns
—
8
—
10
—
12
ns
—
4
—
5
—
6
ns
0
—
0
—
0
—
ns
0
4
0
5
0
6
ns
3
—
3
—
3
—
ns
0
4
0
5
0
6
ns
0
—
0
—
0
—
ns
—
8
—
10
—
12
ns
Notes:
1.  Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V load-
ing specified in Figure 1.
2.  Tested with the loading specified in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
-20 ns -25 ns -35 ns -45 ns
Symbol Parameter Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
trc
Read Cycle Time
20 —
25 —
35 —
45 —
ns
taa
Address Access Time
— 20
— 25
— 35
— 45
ns
toha
Output Hold Time
2.5 —
6—
8—
10 —
ns
tace
CE Access Time
— 20
— 25
— 35
— 45
ns
tdoe
OE Access Time
—8
— 12
— 15
— 20
ns
thzoe⁽²⁾ OE to High-Z Output
08
08
0 10
0 15
ns
tlzoe⁽²⁾ OE to Low-Z Output
0—
0—
0—
0
—
ns
thzce⁽² CE to High-Z Output
08
08
0 10
0 15
ns
tlzce⁽²⁾ CE to Low-Z Output
3—
10 —
10 —
10 —
ns
Notes:
1.  Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2.  Tested with the load in Figure 1b.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011