IS63WV1288DALL Datasheet, PDF (10/20 Pages) Integrated Silicon Solution, Inc – 128K x 8 HIGH-SPEED CMOS STATIC RAM

IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)

Symbol
Parameter
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time to
Write End
tha
Address Hold from
Write End
tsa
Address Setup Time
tpwe₁₍₁₎
tpwe₂₍₂₎
tsd
WE Pulse Width (OE High)
WE Pulse Width (OE Low)
Data Setup to Write End
thd
Data Hold from Write End
thzwe⁽²⁾
WE LOW to High-Z Output
tlzwe⁽²⁾
WE HIGH to Low-Z Output
-8 ns
-10 ns
-12 ns
Min. Max.
Min. Max.
Min. Max.
Unit
8—
10 —
12 —
ns
7—
7—
8—
ns
8—
8—
8—
ns
0—
0—
0—
ns
0—
0—
0—
ns
7—
7—
8—
ns
8—
10 —
12 —
ns
5—
5—
6—
ns
0—
0—
0—
­ns
—4
—5
—6
ns
3—
3—
3—
ns
Notes:
1.  Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)

-20 ns -25 ns -35 ns
Symbol Parameter Min. Max.
Min. Max.
Min. Max.
twc
Write Cycle Time
20 —
25 —
35 —
tsce
CE to Write End
12 —
18 —
25 —
taw
Address Setup Time
to Write End
12 —
15 —
25 —
tha
Address Hold from Write End 0 —
0—
0—
tsa
Address Setup Time
0—
0—
0—
tpwe1 WE Pulse Width (OE = HIGH) 12 —
18 —
30 —
tpwe2 WE Pulse Width (OE = LOW) 17 —
20 —
30 —
tsd
Data Setup to Write End
9—
12 —
15 —
thd
Data Hold from Write End
0—
0—
­0 —
thzwe⁽³⁾ WE LOW to High-Z Output
—9
— 12
— 20
tlzwe⁽³⁾ WE HIGH to Low-Z Output
3—
5—
5—
-45ns
Min. Max. Unit
45 —
ns
35 —
ns
35 —
ns
0—
ns
0—
ns
35 —
ns
35 —
ns
20 —
ns
0—
ns
— 20
ns
5—
ns
Notes:
1.  Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a.
2.  Tested with the load in Figure 1b.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW.All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
12/15/2011