IS61QDB42M18A Datasheet, PDF (8/30 Pages) Integrated Silicon Solution, Inc – Synchronous pipeline read with late write operation

IS61QDB42M18A
IS61QDB41M36A
Application Example
In the following application example, the second pair of C and C# clocks is delayed such that the return data meets the
data setup and hold times at the memory controller.
Data-Out
Address
Read Control
Write Control
Byte Write Control
Source CLK
Return CLK
Source CLK#
Return CLK#
Memory
Controller
Data-In
SRAM #1 CQ Input
SRAM #1 CQ# Input
SRAM #4 CQ Input
SRAM #4 CQ# Input
Vt _{R R}
R
Vt Vt
R = 50Ω
Vt = V REF
Vt Vt
RR
D
SA
R#
W#
BWx#
K
C
K#_{SRAM #1}
C#
Q
CQ
CQ#
ZQ
RQ = 250Ω
D
SA
R#
W#
BWx#
K
C
K#_{SRAM #4}
C#
Q
CQ
CQ#
ZQ
RQ = 250Ω
Integrated Silicon Solution, Inc.- www.issi.com
8
Rev. B
10/02/2014