IS61QDB42M18A Datasheet, PDF (6/30 Pages) Integrated Silicon Solution, Inc – Synchronous pipeline read with late write operation

IS61QDB42M18A
IS61QDB41M36A
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
Power-Up and Power-Down Sequences
The recommendation of voltage apply sequence is : V_DD → V_DDQ ¹⁾→V_REF2)→ V_IN
Notes:
V_DDQ can be applied concurrently with V_DD.
V_REF can be applied concurrently with V_DDQ.
After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKC-
lock cycle period, device initializes internal logics and locks DLL. Depending on /Doff status, locking DLL will be
skipped. The following timing pictures are possible examples of power up sequence.
Sequence1. /Doff is fixed low
After tKC-lock cycle of stable clock, device is ready for normal operation.
Power On stage Unstable Clock Period
Stable Clock period
Read to use
K
K#
VDD
VDDQ
>tKC-lock for device initialization
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
Sequence2. /Doff is controlled and goes high after clock being stable.
Power On stage
Unstable Clock Period
Stable Clock period
K
K#
Read to use
Doff#
VDD
VDDQ
VREF
>tKC-lock for device initialization
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
Integrated Silicon Solution, Inc.- www.issi.com
6
Rev. B
10/02/2014