IS61QDB42M18A Datasheet, PDF (18/30 Pages) Integrated Silicon Solution, Inc – Synchronous pipeline read with late write operation

IS61QDB42M18A
IS61QDB41M36A
AC Timing Characteristics
(Over the Operating Temperature Range, V_DD=1.8V±5%, V_DDQ=1.5V/1.8V)
Parameter
Symbol
25 (400MHz)
Min Max
30 (333MHz)
Min Max
Clock
Clock Cycle Time (K, K#,C,C#)
tKHKH
2.50 8.4 3.00 8.4
Clock Phase Jitter (K, K#,C,C#)
tKC var
0.3
0.3
Clock High Time (K, K#,C,C#)
tKHKL
0.4
0.4
Clock Low Time (K, K#,C,C#)
tKLKH
0.4
0.4
Clock to Clock (K_H→ K#_H, C_H→ C#_H)
tKHK#H
1.10
1.35
Clock to Data Clock (K > C, K# > C#)
tKHCH
0
1.10
0
1.35
DLL Lock Time (K,C)
tKC lock
1024
1024
Doff Low period to DLL reset
tDoffLowToReset
5
5
K static to DLL reset
Output Times
tKCreset
30
30
C,C# High to Output Valid
C,C# High to Output Hold
C,C# High to Echo Clock Valid
C,C# High to Echo Clock Hold
CQ, CQ# High to Output Valid
CQ, CQ# High to Output Hold
C,C# High to Output High-Z
C,C# High to Output Low-Z
Setup Times
tCHQV
tCHQX
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
tCHQX1
0.45
0.45
-0.45
-0.45
0.45
0.45
-0.45
-0.45
0.30
0.30
-0.30
-0.30
0.45
0.45
-0.45
-0.45
Address valid to K rising edge
tAVKH
0.40
0.40
R#,W# control inputs valid to K rising
edge
tIVKH
0.40
0.40
BW_x# control inputs valid to K rising
edge
tIVKH2
0.28
0.30
Data-in valid to K, K# rising edge
tDVKH
0.28
0.30
Hold Times
K rising edge to address hold
tKHAX
0.40
0.40
K rising edge to R#,W# control inputs
hold
tKHIX
0.40
0.40
K rising edge to BW_x# control inputs
hold
tKHIX2
0.28
0.30
K, K# rising edge to data-in hold
tKHDX
0.28
0.30
33 (300MHz)
Min Max
3.33 8.4
0.3
0.4
0.4
1.50
0
1.48
1024
5
30
0.45
-0.45
0.45
-0.45
0.30
-0.30
0.45
-0.45
0.40
0.40
0.30
0.30
0.40
0.40
0.30
0.30
40 (250MHz)
Min Max
4.00 8.4
0.3
0.4
0.4
1.80
0
1.8
1024
5
30
0.45
-0.45
0.45
-0.45
0.30
-0.30
0.45
-0.45
0.40
0.40
0.30
0.30
0.40
0.40
0.30
0.30
unit
ns
ns
cycle
cycle
ns
ns
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
notes
4
5
1,3
1,3
1
1
1,3
1,3
1,3
1,3
2
2
2
2
2
2
2
2
Notes:
1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
6. The data sheet parameters reflect tester guard bands and test setup variations.
7. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
Integrated Silicon Solution, Inc.- www.issi.com
18
Rev. B
10/02/2014