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IS61LV12816 Datasheet, PDF (8/12 Pages) Integrated Circuit Solution Inc – 128K x 16 HIGH-SPEED CMOS STATIC RAM | |||
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IS61LV12816
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter
-10 ns
Min. Max.
-12 ns
-15 ns
Min. Max. Min. Max. Unit
tWC Write Cycle Time
10 â
12 â
15 â
ns
tSCE CE to Write End
8â
8â
10 â
ns
tAW Address Setup Time
to Write End
8â
8â
10 â
ns
tHA Address Hold from Write End
0â
0â
0â
ns
tSA Address Setup Time
0â
0â
0â
ns
tPWB LB, UB Valid to End of Write
8â
9â
10 â
ns
tPWE1 WE Pulse Width (OE = HIGH)
7
â
8â
10 â
ns
tPWE2 WE Pulse Width (OE = LOW)
8â
10 â
11 â
ns
tSD Data Setup to Write End
5â
6â
7â
ns
tHD Data Hold from Write End
0â
0â
0â
ns
tHZWE(3) WE LOW to High-Z Output
â4
â5
â6
ns
tLZWE(3) WE HIGH to Low-Z Output
0â
0â
0â
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0V to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must
be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup
and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
8
Integrated Silicon Solution, Inc. â 1-800-379-4774
Rev. C
02/05/2003
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