IS61LV12816 Datasheet, PDF (5/12 Pages) Integrated Circuit Solution Inc – 128K x 16 HIGH-SPEED CMOS STATIC RAM

IS61LV12816
CAPACITANCE⁽¹⁾
Symbol Parameter
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
COUT
Input/Output Capacitance
VOUT = 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
ISSI ^®
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
-10 ns
-12 ns
-15 ns
Symbol Parameter
Min. Max. Min. Max. Min. Max.
Unit
tRC Read Cycle Time
10 —
12 —
15
—
ns
tAA Address Access Time
— 10
— 12
—
15
ns
tOHA Output Hold Time
3—
3—
3
—
ns
tACE CE Access Time
— 10
— 12
—
15
ns
tDOE OE Access Time
—4
—5
—
6
ns
tHZOE⁽²⁾ OE to High-Z Output
—4
—5
0
6
ns
tLZOE⁽²⁾ OE to Low-Z Output
0—
0—
0
—
ns
tHZCE⁽²⁾ CE to High-Z Output
04
05
0
8
ns
tLZCE⁽²⁾ CE to Low-Z Output
3—
3—
3
—
ns
tBA LB, UB Access Time
—4
—5
—
6
ns
tHZB⁽²⁾ LB, UB to High-Z Output
04
05
0
6
ns
tLZB⁽²⁾ LB, UB to Low-Z Output
0—
0—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input
pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. C
02/05/2003