IS43TR16256A-15HBL Datasheet, PDF (77/88 Pages) Integrated Silicon Solution, Inc – 512Mx8, 256Mx16 4Gb DDR3 SDRAM

IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
9.5.10 Address / Command Setup, Hold and Derating
9.5.10.1 Nominal slew rate and tVAC for setup time tIS(left) and hold time tIH(right) – ADD/CMD with respect to clock
CK#
CK#
CK
CK
tIS tIH
tIS tIH
tIS tIH
tIS tIH
VDDQ
tVAC
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
Setup slew Rate @
Falling signal
=
[VREF(dc)-VIL(ac)max]
/ ΔTF
Nominal
slew rate
Nominal
slew rate
VIL(dc)MAX
VIL(ac)MAX
tVAC
Setup slew Rate @ Rising
signal
=
[VIH(ac)min-VREF(dc)]
/ ΔTR
VSS
TF
TR
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
Hold slew Rate @
Rising signal
=
[VREF(dc)-VIL(dc)max]
/ ΔTR
Nominal
slew rate
Nominal
slew rate
tVAC
Hold slew Rate @
Falling signal
=
[VIH(dc)min-VREF(dc)]
/ ΔTF
VSS
TR
TF
9.5.10.2 Tangent line for setup time tIS(left) and hold time tIH(right) - ADD/CMD with respect to clock
CK#
CK#
CK
CK
tIS tIH
tIS tIH
tIS tIH
tIS tIH
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
Nominal ^tVAC
Setup slew Rate @ slew rate
Falling signal
= tangent line
[VREF(dc)-VIL(ac)max]
/ ΔTF
tangent
line
tangent
line
Setup slew Rate @
Rising signal
= tangent line
[VIH(ac)min-VREF(dc)]
/ ΔTR
VIL(ac)MAX
Nominal
slew rate
VSS
tVAC
TR
TF
VDDQ
VIH(ac)MIN
VIH(dc)MIN
VREF(dc)
VIL(dc)MAX
VIL(ac)MAX
VSS
Hold slew Rate @
Rising signal
= tangent line
[VREF(dc)-VIL(dc)max]
/ ΔTR
tangent
line
Nominal
slew rate
tangent
line
TR
Nominal
slew rate
Hold slew Rate @
Falling signal
= tangent line
[VIH(dc)min-VREF(dc)]
/ ΔTF
TF
Integrated Silicon Solution, Inc. – www.issi.com –
77
Rev. G2
07/28/2016