IS43TR16256A-15HBL Datasheet, PDF (76/88 Pages) Integrated Silicon Solution, Inc – 512Mx8, 256Mx16 4Gb DDR3 SDRAM

IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
9.5.8 Derating values [ps] for DDR3-1866/2133 tIS/tIH - AC/DC based AC125 Threshold
AC125 Threshold -> VIH(ac) = VREF(dc) + 125mV, VIL(ac) = VREF(dc) - 125mV
CK, CK# Differential Slew Rate
DDR3
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2 63 50 63 50 63 50 71 58 79 66 87 74 95 84
1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68
10
0
0
0
0
0
8
8 16 16 24 24 32 34
CMD/ADD ^{0.9 4}
-4
4
-4
4
-4 12
4
20 12 28 20 36 30
Slew Rate 0.8 6
-10
6 -10 6 -10 14
-2 22
6
30 14 38 24
V/ns
0.7 11 -16 11 -16 11 -16 19 -8 27 0 35 8 43 18
0.6 16 -26 16 -26 16 -26 24 -18 32 -10 40 -2 48 8
0.5 15 -40 15 -40 15 -40 23 -32 31 -24 39 -16 47 -6
0.4 13 -60 13 -60 13 -60 21 -52 29 -44 37 -36 45 -26
1.0V/ns
ΔtIS ΔtIH
103 100
82 84
40 50
44 46
46 40
51 34
56 24
55 10
53 -10
9.5.9 Required minimum time tVAC above VIH(ac) {below VIL(ac)} for valid ADD/CMD transition
Slew
Rate
[V/ns]
DDR3
800/1066/1333/1600
175mV
150mV
[ps]
[ps]
1866/2133
135mV
125mV
[ps]
[ps]
DDR3L
800/1066/1333/1600
160mV
135mV
[ps]
[ps]
1866
135mV
125mV
[ps]
[ps]
> 2.0
75
175
168
173
200
213
200
205
2
57
170
168
173
200
213
200
205
1.5
50
167
145
152
173
190
178
184
1
38
130
100
110
120
145
133
143
0.9
34
113
85
96
102
130
118
129
0.8
29
93
66
79
80
111
99
111
0.7
22
66
42
56
51
87
75
89
0.6
Note
30
10
27
13
55
43
59
0.5
Note
Note
Note
Note
Note
10
Note
18
< 0.5
Note
Note
Note
Note
Note
10
Note
18
Note:
The rising input signal shall become equal to or greater than VIH(ac) level; and the falling input signal shall become equal to or less than VIL(ac) level.
Integrated Silicon Solution, Inc. – www.issi.com –
76
Rev. G2
07/28/2016